1. Field of the Invention
The present invention generally relates to digital memory circuits and more specifically to a clamped bit line read circuit.
2. Description of the Related Art
As the process technology enables the fabrication of transistors having smaller dimensions and the density of semiconductor memory devices increases. However, as the process technology shrinks, the reliability of conventional storage cells is reduced due to variations in the process and low operating voltages.
FIG. 1A illustrates a conventional 6 transistor storage cell 100 configured in a memory array, according to the prior art. The 6 transistor storage cell 100 is a conventional static random access memory (SRAM) cell that includes four NMOS transistors and two PMOS transistors. A word line 102, coupled to the gates of two pass transistors may be enabled to read from or write to a storage circuit formed by cross-coupled inverters. The word line 102 is coupled to many 6 transistor storage cells 100 in a row, but only one row is accessed during a read or write operation. When the word line 102 is asserted (driven to a high voltage or TRUE) to perform a read operation, the bit stored in the storage circuit is transferred to bit line H 105 and the complement is transferred to bit line L 106. A sense amplifier 108 amplifies the difference in voltage levels between bit line H 105 and bit line L 106 and the amplified difference, output 109 is sampled to read the bit stored in the 6 transistor storage cell 100.
One problem that results from the low operating voltages is that read operations may be unstable when the transistor threshold voltage is too large compared with the operating voltage, leaving little margin for switching. A read disturb fault occurs when the word line 102 is asserted to read a first 6 transistor storage cell 100. The first 6 transistor storage cell 100 or any other 6 transistor storage cell in the row may be inadvertently written when the first 6 transistor storage cell 100 is read. Therefore, the value stored in the second 6 transistor storage cell 100 may be changed (disturbed) during the read of the first 6 transistor storage cell 100. The read disturb fault results from a transistor mismatch caused by the size of the access transistors coupled to bit line H 105 and bit line L 106 is increased to ensure that the 6 transistor storage cell 100 can be reliably written.
FIG. 1B illustrates a conventional 8 transistor storage cell configured in a memory array, according to the prior art. The 8 transistor storage cell 110 is also conventional SRAM cell. The 8 transistor storage cell 110 includes six NMOS transistors and two PMOS transistors and is robust compared with the 6 transistor storage cell 100. Two additional NMOS transistors are used in the 8 transistor storage cell 110 to prevent read disturb faults.
Separate word lines are provided for reading and writing to avoid read disturb faults. A word line write 112 is coupled to the gates of two pass transistors. When a write operation is performed the word line write 112 is asserted and the value to be written is driven on bit line write H 115 and the complement of the value is driven on bit line write L 116. When a read operation is performed to read from a first 8 transistor storage cell 110, the word line read 114 is asserted and the value stored in the 8 transistor storage cell 110 is output to the bit line read 120. The additional transistors in the read path, prevent the transfer of any signal to the storage circuits of the 8 transistor storage cells 110. Therefore, read disturb faults are prevented.
FIG. 1C illustrates a conventional method of performing a read operation for the 6 or the 8 transistor storage cells 100 and 110 shown in FIGS. 1A and 1B, respectively, according to the prior art. At step 150 the bit lines 105 and 106 or bit lines 115 and 116 are precharged to a high voltage level prior to a read operation. At step 155 the precharge is disabled. At step 160 the word line 104 or 114 is asserted to perform the read operation. At step 165, the method determines if a sufficient differential voltage to be sensed, e.g., at least 100 mV, has developed on the bit line(s). When the 6 transistor storage cell 100 is used, either the bit line H 105 or the bit line L 106 will be pulled down towards a low voltage level while the complementary bit line remains at the high voltage level resulting from the precharge. When the 8 transistor storage cell 110 is used, the bit line read 120 will be pulled down towards a low voltage level or will remain at the high voltage level resulting from the precharge. When the bit lines have developed sufficient differential voltage, at step 170 the word line is negated and at step 175 the voltage difference between the bit line H 105 or the bit line L 106 is sensed by the sense amplifier 108 to generate the output 109. When the 8 transistor storage cell 110 is used, at step 170 the bit line read 120 is sensed to read the value.
Accordingly, what is needed in the art are new circuits that, like the 8 transistor storage cell 110, reduce the occurrence of read disturb faults. Additionally, such new circuits should function with a variety of storage cells, e.g., 6 and 8 transistor storage cells, and should not require that the bit lines be precharged prior to each read operation.